As integrated circuit geometry continues to plunge into the deep sub-micron regime, it becomes increasingly difficult to satisfy the requirements of high performance microprocessor applications for both reliability and rapid circuitry speed. One way to increase the control speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Copper (Cu) is considered a viable alternative to aluminum (Al) for metallization patterns, particularly for interconnect systems having smaller dimensions. Cu has a lower bulk resistivity and potentially higher electromigration tolerance than Al. Both the lower bulk resistivity and higher electromigration tolerance improve circuit performance. A conventional approach to forming a Cu interconnection involves the use of damascene processing in which openings are formed in an interlayer dielectric (ILD) and then filled with Cu. Such damascene techniques typically include single as well as dual damascene techniques, the latter comprising forming a via opening in communication with a trench opening and simultaneously filling by metal deposition to form a via in communication with a metal line.
However, Cu is a mid-gap impurity in silicon and silicon dioxide. Accordingly, Cu diffusion through interlayer dielectrics, such as silicon dioxide, degrades the performance of the integrated circuit. A conventional approach to the diffusion problem comprises depositing a barrier material to encapsulate the Cu line. Typically diffusion barrier materials include tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium-tungsten (TiW), tungsten nitride (WN), Ti—TiN, Titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN) and silicon nitride for encapsulating Cu. The use of such barrier materials to encapsulate Cu is not limited to the interface between the Cu and the ILD, but includes interfaces with other metals as well. In depositing Cu by electroless deposition or electroplating, a seedlayer is also typically deposited to catalyze electroless deposition or to carry electric current for electroplating. For electroplating, the seedlayer must be continuous. However, for electroless plating, very thin catalytic layers can be employed in the form of eyelets.
Conventional Cu interconnect methodology typically comprises planarizing after Cu deposition, as by chemical-mechanical polishing (CMP), such that the upper surfaces of the filled trenches are substantially coplanar with the upper surface of the ILD. Subsequently a capping layer, such as silicon nitride, is deposited to complete encapsulation of the Cu inlaid metallization. However, adhesion of such a capping layer as to the Cu inlaid metallization has been problematic, and Cu diffusion along the surface of the interface with the capping layer has been found to be a major cause of electromigration failure. There have evolved methods of addressing the capping layer adhesion problem, as by treating the planarized surface of inlaid copper with a plasma containing hydrogen or ammonia to reduce the thin film of copper oxide formed thereon, thereby improving capping layer adhesion.
As device dimensions continue to plunge, there has been observed delamination at the interface between inlaid Cu and a capping layer, such as a nitride capping layer, occurring after patterning a via hole to the underlying line. This delamination between inlaid Cu and the capping layer causes void formation eventually leading to premature electromigration failure.
Accordingly, there exists a need for reliable semiconductor devices comprising Cu metallization with improved electromigration resistance. There exists a particular need for such reliable semiconductor devices having Cu metallization methodology with improved electromigration resistance comprising metal levels with varying line widths in the deep sub-micron regime.